A typical current mirror circuit is constructed with transistors having bases coupled together and emitters coupled together. As shown in FIG. 13, a current mirror circuit 1 disclosed in U.S. 2004/0189323A1 corresponding to JP-2004-301670A includes four transistors Q1-Q4. The transistors Q1-Q4 have bases coupled together and emitters connected to a power supply line 2. The current mirror circuit 1 further includes a pullup resistor R1 connected between the bases and the power supply line 2. Each of the transistor Q2-Q4 supplies a collector current Ib to a control circuit 4. The collector current Ib depends on a constant current Ia output from a constant current source 3.
When an integrated circuit (IC) having the current mirror circuit 1 switches to sleep mode, a switch 5 is opened and the supply of the current 1b to the control circuit 4 is cut off. The resistor R1 clamps the bases of the transistors Q1-Q4 to a certain voltage potential during periods when the switch 5 is opened. In each of the transistors Q1-Q4, if the base potential is not clamped, a depletion zone expands toward a collector region due to punch-through breakdown. As a result, a leak current flows from the emitter to the collector.
Whereas the resistor R1 prevents the leak current, a current flowing through the resistor R1 introduces error into a mirror gain of the current mirror circuit 1. For example, when the constant current source 3 outputs the constant current Ia of 5 microamperes (μA) and the resistor R1 has a resistance of 500 kilohms (kΩ), the current flowing through the resistor R1 is determined as follows:
                              VF                      500            ⁢                                                  ⁢            k            ⁢                                                  ⁢            Ω                          =                              0.7            ⁢                                                  ⁢            V                                500            ⁢                                                  ⁢            k            ⁢                                                  ⁢            Ω                                                            =                      1.4            ⁢                                                  ⁢            µA                          ,            where VF is a forward bias voltage of the transistors Q1-Q4.
As a result, the collector current Ib decreases to 3.6 μA and the mirror gain decreases to 0.72 even through it is preferable that the mirror gain is 1.
Increasing the resistance of the resistor R1 can reduce the error introduced in the mirror gain. However, the resistor R1 of 500 kΩ has a layout area of about 70 micrometers (μm)×70 μm, which is about half of pad size. The layout area of the resistor R1 increases with the increase in the resistance of the resistor R1. Therefore, increasing the resistance of the resistor R1 increases chip size and manufacturing cost of the IC.
A constant current circuit disclosed in JP-2002-149250A generates a constant current using a current mirror circuit. The current mirror circuit includes a resistor and operates based on a voltage drop across the resistor. It is preferable that the resistor has high resistance for low power consumption. However, as described above, increasing the resistance of the resistor increases the chip size and the manufacturing cost.